This course covers the following topics: logic gates, binary number systems, conversion between number systems, Boolean algebra, Karnaugh maps, combinational logic, digital logic design, flip-flops, programmable logic devices (PLDs), counters, registers, memories, and state machines.
This course is of 8 chapters divided into 6 weeks. The student should be aware of the importance of revising the material synchronously with the lectures. The assessment is done by 1 Midterm (week4), lab assignments, and a final exam. Lab emphasizes the use of a schematic entry, the use of a logic simulation design tools, and hardware description languages (mainly VHDL). Lab assignments are design-oriented.
|Weeks 1||Digital Computers & Information||1|
|Week 1 - 2||Combinational Logic Circuits||2|
|Week 2 - 3||Combinational Logic Design||3|
|Week 3 - 4||Combinational Functions and Circuits||4||Midterm (Week 4)|
|Week 5||Arithmetic Functions and Circuits||5|
|Weeks 5 - 6||Sequential Circuits||6|
|Week 6||Registers and Counters||7|
|Week 6||Memory Basics||8|
This lab aims to provide the student with an introductory understanding of practical Logic Design issues. The general concepts to be introduced in this lab will increase the students’ awareness of the available digital hardware design packages
This lab introduces EWB (Electronics Work Bench) and VHDL. This includes describing combinational circuits, sequential circuits, registers and counters in structural and behavioral settings. The assessment is done by 4 assignments due in Weeks 3, 4, 5, 6 and a project.
|Weeks 1||Software Setup|
|Week 2||Binary Numbers and Basic Logic Operations|
|Week 2||Combinational Logic Circuits|
|Week 3||Introduction to VHDL||Assignment I (Week 3)|
|Week 3||VHDL – Structural and Behavioral Descriptions|
|Weeks 4||Arithmetic Functions and Circuits||Assignment II (Week 4)|
|Week 5||Sequential Logic Circuits||Assignment III (Week 5)|
|Week 6||Applications||Assignment IV (Week 6)|
|Week 6||Project||Project (Week 15)|
The lab weighs 30% of the total course grade (4 assignments, a project, and a lab final exam).
[June 18, 2006] Chapters 7 and 8, and assignment 4 are posted.
[June 12, 2006] The project details are now available.
[June 12, 2006] Midterm Grades are posted.
[June 9, 2006] Chapters 5 and 6 are posted.
[June 5, 2006]Chapter 4 is posted.
[June 5, 2006] Assignment 3 is posted.
[May 29, 2006] Assignment 2 is posted.
[May 29, 2006] Chapter 3 is posted.
[May 23, 2006] Assignment 1 is posted.
[May 23, 2006] Chapter 2 is posted.
[May 23, 2006] Tuesday's class will be reserved for groups setup. Classes to resume normally on Wednesday.
[May 15, 2006] Chapter 1 is posted.
[May 15, 2006] If you want to use VHDLSimili from Symphony EDA, from the Symphony EDA Licensing Wizard (Start -> All Programs -> Symphony EDA -> VHDL Simili 2.3 -> License Management) you should activate your free license online. Please note that after installing the package, you must replace the file: symphony.lic, in the directory: C:\Program Files\Symphony EDA\VHDL Simili 2.3\Bin with the file: freelic.txt. In other words, delete the existing symphony.lic, and rename freelic.txt to symphony.lic; make sure the new file is not called symphony.lic.txt!
[May 15, 2006] Peter J. Ashenden, VHDL Tutorial, Elsevier Science, 2004.
[May 15, 2006]Every student should install QUARTUS+II from Altera (www.altera.com), VHDLSimili (From Symphony EDA), and Xilinx ISE 4.2i (Available with the book:Logic and Computer Design Fundamentals, 3rd edition updated, M. Morris Mano and Charles R. Kime, Prentice Hall, 2004).
[May 15, 2006]Welcome to the course website...